Regarding to the TA answer to "Register Access Control", should Address, ASn, R/Wn, UDSn, LDSn serve as outputs of the register access control when the DMA becomes the bus master? When the CPU becomes the bus master, should Address, ASn, R/Wn, UDSn, LDSn become the input of the register access control?

-- Roy Leung (roy.leung@utoronto.ca), February 20, 1999

Answers

The idea is to break your design down into smaller modules that perform specific tasks. This makes design, implementation, and testing much easier.

With this in mind, the Register Access Control block is only ever resposible for being a slave device on the 68000 bus. It controls access (read/write) to the registers. That is all.

The DMA Control block is responsible for the bus master side of things. It drives the bus control lines and tells the address and data register to drive their values when it is appropriate.

-- Steven Caranci (caranci@eecg.toronto.edu), February 22, 1999.