I'm going to give a quick overview of DMA to help clear up questions. In the following you can substitute 'word' for 'byte' throughout if you want.

If you want to transfer data between two devices on the bus (neither one of which is the CPU) then one way of doing it is to have the CPU execute a loop that does the following pseudo-code:

  - poll the source device for a byte being ready
  - read the byte into the CPU
  - write the byte out to the target device.

This is called POLLED I/O for obvious reasons. The drawback is that this is very slow, since the CPU acts as a temporary storage area for each piece of data transferred bewteen the source and target which is unnecessary. (Let's say that a read/write takes 8 Bus Clocks, then the Poll takes 8, the read takes 8 and the write takes 8, using up 24 clock cycles just to transfer one byte, when ideally you should be able to transfer a byte on every Bus clock cycle.)

The code executed by the CPU is simple enough that it is possible to do it in hardware. This DMA engine can go off and do the entire transfer while the CPU does other work and the engine can also do the transfer more efficiently. So now all the CPU needs to do is set up the DMA operation by writing into the DMA engine the following information:

  - the Source Device start address (where to start reading data)
  - the Target Device start address (where to write the data to)
  - the number of bytes of data

then tell it to start. The DMA engine goes off and does the job, and somehow notifies the CPU when it is done. This is usually by means of an interrupt, but in the lab we don't worry about it. You can just verify afterwards that the DMA operation finished successfully.

Normally the source and target locations are the same size (e.g. you would transfer an 8KB block from a disk to memory). In the lab your DMA engine only has a single word buffer. When transferring from your DMA engine to memory, you write out whatever value is currently in the Data Register into COUNT consecutive memory locations. (That is memory will end up containing COUNT copies of the Data Register at the appropriate Target address.) In the other direction you read consecutive memory locations and have each new byte overwrite the existing byte in the Data Register. Thus if memory contains $12, $34, $56 and we do a 3-byte DMA Read (DMA Read/Write are from the point of view of the DMA engine) then the Data Register will get loaded with all 3 values in turn, and it should end up with $56.

You can setup the DMA engine either using a 68K assembly program or (easier) just by hand using Gizmo monitor fill commands to write the control register values.

Note that the DMA engine should have a maximum transfer size of 256 bytes. This would need 8 address bits. However you only need to support word transfers, so you really only need 7 bits (thus the 7 bits in the COUNT register).

The Register Control logic needs to provide the ability to write values into the Address, Count, Control and Data registers. This is similar to the previous labs. The DMA control box then needs to check to see if the Count bits are non-zero, which it considers to be its Start signal. It must then request the bus, wait for bus ownership (i.e. /BG asserted, in addition /AS & /DTACK de-asserted to make sure the last transaction has finished) then assert /BGACK and start doing the DMA transfer.

In Burst Mode /BGACK is held asserted for the whole transfer. In Cycle-Steal mode after each word transferred the DMA control box must de-assert /BGACK and make another bus request as above.

Robin

-- Robin Grindley (grindley@eecg.toronto.edu), February 19, 1999